مشخصات پژوهش

عنوان	All digital fast lock DLL-based frequency multiplier
نوع پژوهش	مقاله چاپ شده
کلیدواژه‌ها	DLL, Delay locked loop, Modified gradient algorithm, Optimization, Multiplier
چکیده	One of the most important parameters in the design of synthesizers is lock time. A new fast lock delay locked loop (DLL) based frequency multiplier is proposed in this paper. Phase detector, charge pump and loop filter in conventional DLLs are replaced by a digital signal processor in the proposed structure. This leads to have better lock time, higher speed and smaller chip aria. The proposed structure can be implemented easily in a real system by means of a suitable powerful digital signal processor. Simulation has been done for 11 delay cells as a delay chain and input frequency equal with 300 MHz. The output frequency is multiplied by 11 (fOUT = 3.3 GHz), and lock time is obtained about 13 ns which is equal to 4 clock cycles of reference clock.
پژوهشگران	غلامرضا اردشیر (نفر چهارم)، حسین میارنعیمی (نفر سوم)، محمد غلامی (نفر دوم)، حمید رحیم پور (نفر اول)