سامانه مدیریت امور پژوهشی دانشگاه مازندران | غلامرضا اردشیر

نام و نام خانوادگی	غلامرضا اردشیر
شغل	عضو هیئت علمی سایر دانشگاه‌های کشور
تحصیلات	_
وبسایت
پست الکترونیک	—

	عنوان	مجله
1	A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor	Microprocessors and Microsystems
2	A low power and jitter delay cell with pulse width modulation for wide range delay lock loops	MICROELECTRONICS JOURNAL
3	Using Universal Nand-nor-inverter Gate to Design D-latch and D Flip-flop in Quantum-dot Cellular Automata Nanotechnology	International journal of Engineering
4	Analysis and design of a low jitter delay-locked loop using lock state detector	INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
5	Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates	INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
6	Phase‑frequency detector in QCA nanotechnology using novel flip‑flop with reset terminal	international nano letters
7	A Low-Power and High-Frequency Phase Frequency Detector for a 3.33-GHz Delay Locked Loop	Circuits, Systems, and Signal Processing
8	A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers	INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
9	Jitter of delay-locked loops due to pfd	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
10	Dual Phase Detector Based on Delay Locked Loop for High Speed Applications	International Journal of Engineering Transactions A: Basics
11	Design of Novel Testable and Diagnosable Phase-Frequency Detector	CIRCUITS SYSTEMS AND SIGNAL PROCESSING
12	All digital fast lock DLL-based frequency multiplier	ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
13	Digital delay locked loop-based frequency synthesiser for Digital Video Broadcasting-Terrestrial receivers	IET Circuits Devices & Systems
14	Analysis of DLL Jitter due to Voltage-Controlled Delay Line	CIRCUITS SYSTEMS AND SIGNAL PROCESSING
15	A novel architecture for low voltage-low power DLL-based frequency multipliers	IEICE Electronics Express
16	Low‐power and wide‐band delay‐locked loop with switching delay line	INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
17	Low Settling Time All DigitalDLL for VHF Application	international journal of engineering
18	طراحی ضرب کننده فرکانسی بر اساس حلقه قفل شده تاخیر دیجیتالی و با سرعت بالا	مهندسي برق و الكترونيك ايران