2024 : 5 : 5
Mohammad Gholami

Mohammad Gholami

Academic rank: Associate Professor
ORCID:
Education: PhD.
ScopusId:
Faculty: Faculty of Technology and Engineering
Address: http://scimet.umz.ac.ir/Mohammad_Gholami
Phone: 01135302904

Research

Title
Low Settling Time All DigitalDLL for VHF Application
Type
JournalPaper
Keywords
DLL, Delay Locked Loop, PRP Conjugate Gradient Algorithm, Optimization, Multiplier.
Year
2015
Journal international journal of engineering
DOI
Researchers Mohammad Gholami ، hamid Rahimpour ، Gholamreza Ardeshir ، Hossein Miar Naimi

Abstract

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of each delay cells. Since this novel architecture has removed phase detector, charge pump and loop filter, the proposed structure shown occupy smaller chip area and has less settling time than conventional DLLs. This method could be implemented in a real system by means a digital signal processor device. Simulation has been done for 15 delay cells and fREF is chosen 14MHz to have output frequency 14×15=210MHz. fOUT=210 MHz is one of the channels in Iran VHF frequency band. As shown with simulations, the proposed architecture has locking time approximately 286nsec which is equal to 4 clock cycles of reference clock.