Title
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Jitter of delay-locked loops due to pfd
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Type
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JournalPaper
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Keywords
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Delay-locked loop (DLL), jitter, phase noise, phase-locked loop (PLL)
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Abstract
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In this paper, delay-locked loop's (DLLs) jitter due to uncertainties in the phase frequency detector (PFD) is calculated. First, time-domain equations of the DLL are introduced. These equations are the key to obtaining a closed-form equation related to the jitter of DLL in presence of a noisy PFD. Jitter equations at the output of all stages are calculated theoretically. A DLL is designed in 0.18-μm CMOS technology to validate the obtained equations.
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Researchers
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Gholamreza Ardeshir (Second Researcher), Mohammad Gholami (First Researcher)
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