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Title
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All digital fast lock DLL-based frequency multiplier
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Type
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JournalPaper
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Keywords
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DLL, Delay locked loop, Modified gradient algorithm, Optimization, Multiplier
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Abstract
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One of the most important parameters in the design of synthesizers is lock time. A new fast lock delay locked loop (DLL) based frequency multiplier is proposed in this paper. Phase detector, charge pump and loop filter in conventional DLLs are replaced by a digital signal processor in the proposed structure. This leads to have better lock time, higher speed and smaller chip aria. The proposed structure can be implemented easily in a real system by means of a suitable powerful digital signal processor. Simulation has been done for 11 delay cells as a delay chain and input frequency equal with 300 MHz. The output frequency is multiplied by 11 (fOUT = 3.3 GHz), and lock time is obtained about 13 ns which is equal to 4 clock cycles of reference clock.
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Researchers
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Gholamreza Ardeshir (Fourth Researcher), Hossein Miar Naimi (Third Researcher), Mohammad Gholami (Second Researcher), hamid Rahimpour (First Researcher)
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