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Abstract
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This paper presents a time-domain model for general jitter analysis of delay-locked loops (DLLs). According to this model, the noise contribution of each part of the circuit is specified at the output of DLL, and a closed-form relationship is extracted. By this closed-form relationship, we show that accumulated jitter, known as jitter peaking, always exists due to the loop filter capacitor in a widely used DLL configuration. The effect of jitter accumulation can cause an unstable lock state. A conventional DLL is simulated in 0.18 µm CMOS technology to verify the closed-form relationship.
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