This paper describes a symmetric phase frequency detector (PFD). The symmetric structure of PFD provides phase-locked loop (PLL) functions with a low jitter. The most important point in designing PFDs is attention to their dead zone, the extent of their linearity, and the frequency range of operation. As the dead zone of a phase detector circuit is smaller, this circuit is capable of detecting fewer phase differences in high frequencies. In this paper, considering the trade-off between the dead zone and the maximum operating frequency, the highest operating frequency is achieved with minimal dead zone design. Post-layout simulation for TSMC 0.13 μm technology is performed using the CMOS technology: The results so obtained are then compared with existing literature. These results indicate a power consumption of less than 90μW and a frequency response of 4.1 GHz, as well as a dead zone of less than 25 ps in the worst case: This is a suitable condition as compared to previous, related works. The area of the proposed symmetric circuit is 250 μm2. Finally, the proposed PFD tested in PLL and the results indicate that the structure is useful for frequency synthesizer applications.
