A low‐power and wide‐band delay‐locked loop (DLL) is presented. Switching the delay line is used to enhance the input frequency range of the DLL. First delay line with short delay times is designed for high frequencies, and second delay line with long delay times is designed for low frequencies. Also, a switching circuit is used to control the delay lines. Proposed delay lines give delay range 0.5 to 34 nanoseconds in which DLL can operate input frequency range of 30 MHz to 2 GHz. This DLL has been simulated in 0.18‐μm CMOS technology. The simulated root‐mean‐square and peak‐to‐peak jitters are 3.12 and 11.03 picoseconds at 2 GHz, respectively. The power dissipation at 2 GHz is 3.24 mW for a supply voltage of 1.8 V.
