Today, due to the impossibility of further reducing the dimensions, electronic devices are faced with fundamental challenges in parameters such as speed, frequency, and power consumption for CMOS technology circuit. One solution is to replace CMOS technology with other technologies such as Quantum-dot Cellular Automata (QCA) technology. Extensive researches have been done for design digital circuits in QCA technology. Phase-frequency detector (PFD) is one of the main blocks in electrical and communication systems. In this paper, a structure is presented for a PFD in QCA technology for the first time. In the proposed structure, a D flip-flop (D-FF) with reset ability based on a new inverter gate is used. The new inverter gate of this D-FF compared to previous inverters, has output signal with high polarization level. Also, the proposed PFD has 199 cells, 0.22 μm2 occupied area and two clock cycles latency that is smaller compared with PFD which is designed with the conventional inverter.
