In this paper, a new circuit to synthesise negative capacitor by using MOSFETs is proposed. This circuit has been analysed exactly. Output admittance, value of negative capacitor and frequency limitations of proposed architecture, has been investigated accurately and related equations are obtained theoretically in presence of all parasitic capacitors. Also, this new negative capacitor structure is simulated in TSMC 0.13 µm CMOS Technology. Simulation results confirm the analytical predictions. By variation of gm and CX in proposed architecture, negative capacitor can be obtained in higher frequencies up to 15 GHz.
