Static random access memories (SRAMs) are vital parts in digital circuits. The fast growth of battery-operated devices has caused methods for reducing power consumption in the memories to be important. SRAMs spend most of the time in hold state, and with their enlarging size, reducing static power becomes important. In this paper, two new low-voltage, 8- and 9-transistor cells with separate read/write path and the use of transistors with different threshold have been resented. These cells achieve a significant reduction in the static power and increase in read static noise margin (RSNM), and improvement in reading and writing speed, as compared to the conventional 7T and 9T cells. Static power of the first proposed cell is improved by 64.76 and 69.94% compared to the 7T cell and 9T cell, respectively. Also, this parameter for the second proposed cell is 66.87 and 71.74%, respectively. RSNM of the first proposed cell is improved by 121.66% compared to the 7T cell and 9T cell, and this parameter for the second proposed cell is 40.83%. In addition, the read time of two proposed cells is improved by almost 75% compared to that of the 9T cell. The write time of the first proposed cell is improved by 25.11 and 19.16% compared to that of the 7T cell and the 9T cell, respectively. This parameter for the second proposed cell is 31.74 and 26.26% compared to the 7T cell and 9T cell, respectively. In order to evaluate the performance of the proposed cells, simulations have been done in TSMC 130 nm CMOS technology with a supply voltage of 0.7 V.
