To reach a delay lock loop (DLL) with low jitter and power for wide range frequency applications, the performance of delay cell used in the voltage-controlled delay line (VCDL) play the most important role. In recent years, a variety of methods have been proposed to achieve a wide-range delay cell. In this paper, a method is proposed in which pulse width modulation (PWM) technique is used to generate a wide-range delay it is in a better trade-off with power and jitter with respect to previous work. PWM circuit creates two control signal (rising and falling control signal) for last stage transistors. These control signals generate a signal that is similar to the input signal of the delay cell with a controllable delay. The proposed delay cell is able to generate a delay that is more than half of the input clock period leads to a wideband DLL. The delay cell has been simulated in TSMC RF CMOS 0.18 μm technology at 1.8 V supply voltage. The simulation results show that the desired structure has a delay range of 195 ps to 3.4 ns in a frequency range 300 MHz to 1 GHz. Moreover, its RMS jitter is equal to 2–22 ps, 0.33 ps at 300 MHz and 1 GHz, respectively.
