محمد غلامی

Lock time and convergence time are the most important challenges in delay‐locked loops (DLLs). In this paper we cover French very high frequency band with a novel all‐digital fast‐lock DLL‐based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells, and fREF = 16 MHz, which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.3 µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure.