In this paper, a new CMOS LC Series Coupled Quadrature Oscillator (SC-QO) is proposed with desirable phase noise performance and low power consumption. The complementary switching pairs are employed to compensate the loss of LC tanks and also provide high transconductance in order to prevent much current to be consumed and more symmetric oscillation condition provided by them. The phase noise as a critical factor for specifying the SC-QO’s performance is improved via various applied techniques. The main idea of this paper is based on the stacked and cascoded transistors which are shaped at the top of the proposed SC-QO’s structure to predominate the challenge of voltage headroom and power consumption and proposed a method to provide a current doubler .Two current doublers are placed cascoded, the upper doubler increases the current and the lower doubler increases it further. In this way, two DC current paths are reusing current and the input DC current doubled two times by them. According to the proposed idea of this paper the phase noise is improved while the consumption-power is reduced by four-folding DC current and the power efficiency increased, consequently. Therefore, the improvement of the proposed SC-QO’s phase noise could be proven from another aspect of designing and by the linear time variant theory that the phase noise performance could be improved by reducing DC power consumption. To evaluate the validity of proposed QO, a designed SC-QO simulated using the practical 0.18 m TSMC CMOS technology at 4.039 GHz fundamentalfrequency. The SC-QO consumes1.102 mW from a 1.8V power supply, phase noise is -122.010 (dBc/Hz) @1 MHz and - 131.595 (dBc/Hz) @3 MHz offset frequencies with the quality factor (Q=10.5) and is desirable. The Figure of Merit (FOM) of -193.71 (dBc/Hz) achieved. The obtained simulation results confirm the reliablity of the proposed SC-QO.
