2024 : 11 : 1
Ali Bahari

Ali Bahari

Academic rank: Professor
ORCID:
Education: PhD.
ScopusId:
HIndex:
Faculty: Science
Address:
Phone: 9112537702

Research

Title
The low threshold voltage n-type silicon transistors based on a polymer/silica nanocomposite gate dielectric: The effect of annealing temperatures on their operation
Type
JournalPaper
Keywords
Nanocomposite N-type silicon transistor; Gate dielectric; Annealing process; Threshold voltage
Year
2017
Journal Applied Surface Science
DOI
Researchers Adeleh Hashemi ، Ali Bahari ، Shahram Ghasemi

Abstract

In this work, povidone/silica nanocomposite dielectric layers were deposited on the n-type Si (100) substrates for application in n-type silicon field-effect transistors (FET). Thermogravimetric analysis (TGA) indicated that strong chemical interactions between polymer and silica nanoparticles were created. In order to examine the effect of annealing temperatures on chemical interactions and nanostructure properties, annealing process was done at 423–513 K. Atomic force microscopy (AFM) images show the very smooth surfaces with very low surface roughness (0.038–0.088 nm). The Si2p and C1s core level photoemission spectra were deconvoluted to the chemical environments of Si and C atoms respectively. The obtained results of deconvoluted X-ray photoelectron spectroscopy (XPS) spectra revealed a high percentage of silanol hydrogen bonds in the sample which was not annealed. These bonds were inversed to stronger covalence bonds (siloxan bonds) at annealing temperature of 423 K. By further addition of temperature, siloxan bonds were shifted to lower binding energy of about 1 eV and their intensity were abated at annealing temperature of 513 K. The electrical characteristics were extracted from current-Voltage (I-V) and capacitance-voltage (C-V) measurements in metal-insulator-semiconductor (MIS) structure. The all n-type Si transistors showed very low threshold voltages (−0.24 to 1 V). The formation of the strongest cross-linking at nanostructure of dielectric film annealed at 423 K caused resulted in an un-trapped path for the transport of charge carriers yielding the lowest threshold voltage (0.08 V) and the highest electron mobility (45.01 cm2/V s) for its FET. By increasing the annealing temperature (473 and 513 K) on the nanocomposite dielectric films, the values of the average surface roughness, the capacitance and the FET threshold voltage increased and the value of FET electron field-effect mobility decreased.